Altera Quartus VHDL Simulation Binary Arithmetic

Design Binary Arithmetic Components

1 bit Half Adder – constructed with all NANDs

1 bit Full Adder – constructed with all NANDs

4 bit Adder – constructed with all full adders

8 bit Adder – constructed with 4 bit adders

16 bit Adder – constructed with 8 bit adders

Test circuit using Value -> Arbitrary Value to set particular values for the inputs during a time period of the timing diagram to test the circuit with a set of specific inputs

Build using hierarchical design using PACKAGE and COMPONENT

Build using arrays of bits using STD_LOGIC_VECTOR type

Lab 2
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Date
Part 1: A 1-bit Half Adder to add 2 binary bits (A, B) and results in a 1-bit Sum and 1-bit Carry-out (Cout)
with only NAND gates.
Project Settings Snip
Truth Table
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Project Wizard
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Add your
Truth Table
HERE
K-maps and Simplest Sum of Products
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K-maps and Simplest SoP
HERE
Drawing Simplest NAND Circuit equivalent the Simplest Sum of Products
Add your
Simplest NAND Circuit HERE
VHDL Code
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VHDL Code HERE
Successful Compilation
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Successful Compilation
Screenshot HERE
Timing Diagram
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Timing Diagram with
annotating matches Truth
Table HERE
Part 2: A 1-bit Full Adder to add 2 binary bits (A, B) and a 1-bit Carry-in (Cin) and results in a 1-bit Sum and
1-bit Carry-out (Cout) with only NAND gates.
Project Settings Snip
Truth Table
Add your
Project Wizard
Settings snip
HERE
Add your
Truth Table
HERE
K-maps and Simplest Sum of Products
Add your
K-maps and Simplest SoP
HERE
Drawing Simplest NAND Circuit equivalent the Simplest Sum of Products
Add your
Simplest NAND Circuit HERE
VHDL Code
Add your
VHDL Code HERE
Successful Compilation
Add your
Successful Compilation
Screenshot HERE
Timing Diagram
Add your
Timing Diagram with
annotating matches Truth
Table HERE
Part 3: A 4-bit Adder to add 2 4 bit binary numbers (A3,A2,A1,A0 and B3,B2,B1,B0 with A0 and B0 being least
significant bits) and a 1-bit Carry-in (Cin), and results in a 4-bit Sum (S3,S2,S1,S0) and 1-bit Carry-out (Cout)
with the 1-bit Full Adder component you built.
Project Settings Snip
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Project Wizard
Settings snip
HERE
Draw of your circuit
Add your
Circuit HERE
VHDL Code
Add your
VHDL Code HERE
Successful Compilation
Add your
Successful Compilation
Screenshot HERE
Timing Diagram
Add your
Timing Diagram with
annotating matches Truth
Table HERE
Part 4: A 8-bit Adder to add 2 8-bit binary numbers (A7,A6,A5,A4,A3,A2,A1,A0 and B7,B6,B5,B4,B3,B2,B1,B0
with A0 and B0 being least significant bits) and a 1-bit Carry-in (Cin), and results in a 4-bit Sum
(S7,S6,S5,S4,S3,S2,S1,S0) and 1-bit Carry-out (Cout) with the 1-bit Full Adder component you built.
Project Settings Snip
Draw your circuit HERE
Add your
Project Wizard
Settings snip
HERE
Add your
Circuit HERE
VHDL Code
Add your
VHDL Code HERE
Successful Compilation
Add your
Successful Compilation
Screenshot HERE
Timing Diagram
Add your
Timing Diagram with
annotating matches Truth
Table HERE
Part 5: A 16-bit Adder to add 2 16-bit binary numbers(A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
and B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0 with A0 and B0 being least significant bits)
and a 1-bit Carry-in (Cin), and results in a 16-bit Sum (S15,S14,S13,S12,S11,S10,S9,S8,S7,S6,S5,S4,S3,S2,S1,
S0) and 1-bit Carry-out (Cout) with component you built
Project
P
Settings Snip
r
Draw your circuit Here
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Project Wizard
Settings snip
HERE
VHDL Code
Add your
VHDL Code HERE
Add your
Circuit
HERE
Successful Compilation
Add your
Successful Compilation
Screenshot HERE
Timing Diagram
Add your
Timing Diagram with
annotating matches Truth
Table HERE